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1. Field of the Invention
The field of the present invention generally relates to electronic design automation and testing of integrated circuits, and, more particularly, to methods and systems for testing circuit blocks in multi-block chip designs.
2. Background
Chip designers often use electronic design automation (EDA) software tools to assist in the design process, and to allow simulation of a chip design prior to prototyping or production. Chip design using EDA software tools generally involves an iterative process whereby the chip design is gradually perfected. Typically, the chip designer builds up a circuit by inputting information at a computer workstation generally having high quality graphics capability so as to display portions of the circuit design as needed. A top-down design methodology is commonly employed using hardware description languages (HDLs), such as Verilog(copyright) or VHDL, for example, by which the designer creates an integrated circuit by hierarchically defining functional components of the circuit, and then decomposing each component into smaller and smaller components.
The various components of an integrated circuit are initially defined by their functional operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation. The logic cells are then xe2x80x9cplacedxe2x80x9d (i.e., given specific coordinate locations in the circuit layout) and xe2x80x9croutedxe2x80x9d (i.e., wired or connected together according to the designer""s circuit definitions) using specialized placement and routing software, resulting in a physical layout file. A mask file, for example a GDSII or CIF format, may be provided to a foundry, and contains enough information to allow the foundry to manufacture an actual integrated circuit therefrom.
At various stages of the design process, validation of the design may be desired through test or verification procedures. To test a design, a set of test vectors is ordinarily generated which will be applied to the inputs to the design and compared against the outputs of the design. An error in the design will be indicated if the actual output generated by the design does not match the expected output. A test access port (TAP) is usually provided on-chip for receiving input test data from a test data source and outputting output test data from the integrated circuit. The test access port is generally used for testing an integrated circuit during and after the manufacturing of the integrated circuit. Another common use of the test access port is on a printed circuit board (PCB) where interconnectivity between multiple components (ICs) can be verified in addition to testing the individual components (ICs). The test access port is generally connected to a serially linked set of boundary-scan cells, one such cell for each input and output pin of the integrated circuit. The test access port controls the inflow and outflow of information with respect to the boundary-scan cells, and hence with respect to the integrated circuit core.
Test and verification processes are facing new challenges due to changes in integrated circuit (IC) design. In particular, decreases in the feature size of circuit elements has led to the ability to place more components on a single integrated circuit. At the same time, decreases in design cycle time are being sought, in order to allow faster time-to-market and hence a potential competitive advantage. Due in part to these trends, the current trend in integrated circuit core design is to create more and more complex cores capable of being stored on a single IC. Design cores that were previously whole ICs have now been reduced to sizes allowing their use as individual components of complex ICs containing multiple design cores.
Another trend in the integrated circuit design industry is to reuse pre-existing circuit blocks in a new design, particularly in multi-core integrated circuits, in order to reduce the development time of an integrated circuit. The pre-existing circuit blocks may be xe2x80x9csoftxe2x80x9d or xe2x80x9chardxe2x80x9d, or somewhere in between. A xe2x80x9csoftxe2x80x9d circuit block is one that has not been physically laid out, while a xe2x80x9chardxe2x80x9d circuit block has its physical layout already determined (i.e., placement and routing of its internal components has been achieved). Pre-existing circuit blocks may occasionally be referred to as xe2x80x9cVCsxe2x80x9d (short for xe2x80x9cVirtual Componentsxe2x80x9d) or xe2x80x9cIPsxe2x80x9d (short for xe2x80x9cIntellectual Properties,xe2x80x9d suggesting their proprietary nature to particular designers). Often, pre-existing circuit blocks will include their own individual test access port to allow testing of the IP itself, assuming the test access port is accessible through chip-level pins after the pre-existing circuit block is placed in a larger integrated circuit design.
A conventional approach to complex IC design involves system development using pre-existing circuit cores (e.g., VCs or IPs) which have already been individually tested using manufacturer developed test vectors. Often, a basic IC platform is developed, and as the design functionality is expanded, more pre-existing circuit cores are added to the hierarchy of the design. Reuse of pre-existing integrated circuit cores generally raises the possibility of using the existing manufacturing level test vectors to further reduce total design and verification time. Investing time in developing new test vectors when test vectors already exist for a given virtual component block would defeat the goal of reducing the time-to-market through partial design reuse. This is particularly true if the reused virtual component block is already hardened, leaving little or no room to generate different test vectors.
As the design size and complexity of integrated circuits has increased, the time necessary to develop manufacturing level test vectors has also increased significantly, causing increased delays in delivering the chips to market. To complicate matters further, the widely accepted IC test standard, Standard 1149.1 promulgated by the Institute of Electrical and Electronics Engineers (IEEE), cannot be used directly in ICs containing embedded cores with built-in test access ports. The 1149.1 standard was formulated with the goal of allowing one test access port per chip, and does not take into account the possibility of chip designs containing multiple embedded cores, some of which may already have built-in 1149.1 compliant test access ports. This problem is becoming increasingly significant as the 1149.1 test standard has reached widespread acceptance in the electronics and semiconductor industries, making it highly desirable that current and future ICs be fully compliant with the standard.
Use of existing or even new test vectors to test the individual cores inside multi-core integrated circuits poses difficult challenges because the individual cores are embedded within the chip, with limited or no direct pin access exterior to the chip itself. When the multi-core integrated circuits are manufactured, only necessary external connectivity is maintained; therefore, many of the pins of the of the individual circuit blocks are partially or completely inaccessible from outside the chip. Because external connectivity to each pin of the individual circuit blocks cannot be provided, testing individual circuit blocks by applying a set of test vectors to the manufactured multi-core integrated circuit designs can be problematic. Further, even if the circuit blocks have boundary-scan (BS) ports, and even if the test vectors are designed to test the individual circuit blocks through their boundary-scan ports, it is neither feasible nor efficient to bring the connectivity of the entire boundary-scan port of all such circuit blocks out to the edge of the chip because this would significantly increase the number of test pins at the chip level.
Another problem with testing complex ICs is that some circuit blocks may themselves be comprised of one or more internal circuit blocks, each of which also may require testing, and each of which also may be originally designed with its own design access port. The existing IEEE Standard does not adequately define a protocol suitable for testing circuit blocks internal to a larger circuit block on a chip.
Various methodologies have recently been proposed to address the difficulties associated with testing the embedded cores in complex ICs while still adhering to the IEEE 1149.1 standard. One approach, for example, is described in Lee Whetsel, xe2x80x9cAn IEEE 1149.1 Based Test Access Architecture for ICs With Embedded Cores,xe2x80x9d Proc. International Test Conference, 1997, pp. 69-78, hereby incorporated by reference as if set forth fully herein. The approach detailed in this article, while directed to the problems associated with testing embedded IC cores, requires modification to the existing test access port (TAP) controllers in the circuit blocks, including a large amount of logic (resulting in modified TAP controllers) at each level of core hierarchy. Other methodologies not requiring modifications to existing test access port controllers, and directed primarily to designs having pre-hardened blocks, may require the addition of a modified TAP controller (known as an HTAP) at each circuit block hierarchy level. Such an approach is described in D. Bhattacharya, xe2x80x9cHierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit,xe2x80x9d Proc. VLSI Test Symposium, 16th IEEE, 1998, pp. 8-14, hereby incorporated by reference as if set forth fully herein. The aforementioned conventional approaches may require increased engineering time and effort, due to the complexity of the implementation involved, and may further require specialized software tools.
Another method for testing embedded cores in complex ICs makes use of multiplexers (MUXs) to select a desired circuit block containing the core to be tested. With this approach, the number of select pins needed for multiplexing is generally log2N, rounded up, where N is the number of embedded cores to be tested in the design. Thus, for example, four select pins would be necessary to select one of nine circuit blocks containing an embedded core within a chip, since log29 rounded up is 4. While allowing access to different embedded cores, this technique can be undesirable because it requires a number of chip test pins proportional to the number of cores embedded in the integrated circuit, which becomes inefficient for complex designs containing large numbers of embedded cores.
A need thus exists for a scaleable, efficient mechanism to access embedded cores for testing in complex ICs, particularly one that is compatible with the IEEE 1149.1 standard, that requires minimal design and area overhead, and that interfaces easily with circuit blocks having pre-generated test pattern sequences.
The invention provides in one aspect a method and system for testing multiple-block integrated circuits. A preferred system and method are described that can be compatible with the IEEE 1149.1 standard test protocol.
In one embodiment as disclosed herein, a system and method are provided for testing an integrated circuit comprising one or more circuit blocks, each containing an internal core, and a chip access port (e.g., an IEEE standard 1149.1 compliant test access port) preferably connected to a set of boundary-scan cells. In one aspect, a hierarchical test control network for an integrated circuit, comprises a top-level test control circuit block with a chip access port, and a plurality of lower-level test control circuit blocks connected, directly or indirectly, to the top-level test control circuit block in a hierarchical structure. Each of the lower-level test control circuit blocks may be connected to or part of an individual circuit block within the integrated circuit design, for controlling the testing thereof. In this embodiment, each of the lower-level test control circuit blocks preferably comprises a socket access port (SAP) controller, and test operation is transferred downward and upwards within said hierarchical structure. In a particular embodiment, test operation is transferred downward and upwards within the hierarchical structure by communicating from the present-level test control circuit block to the test control circuit block at the immediately higher or immediately lower hierarchical level in the hierarchical structure.
Each of the lower-level test control circuit blocks may comprise a test mode select input port, a test data input port, and a test data output port. In such a configuration, each of the lower-level test control circuit blocks may comprise a state controller for controlling the receipt or transmission of information from or to the test mode select input port, the test data input port, and the test data output port.
Test control circuit blocks connected at the same hierarchical level may share a common test mode enable input (e.g., TME_IN) signal, a common test reset signal, a common test mode select signal, and a common clock signal, and collectively output a common test mode output (e.g., TME_OUT) signal comprising a logical OR of individual test mode data output signals output from each of the test control circuit blocks connected at the same hierarchical level. In such a configuration, each of the lower-level test control circuit blocks connected at the same hierarchical level may receive separate test mode data in signals from lower-level test control circuit blocks at an immediately lower hierarchical level, and may output separate test mode enable output signals to the lower-level test control circuit blocks at the immediately lower hierarchical level.
Each of the lower-level test control circuit blocks of the hierarchical test control network may be functionally identical. Further, each of the lower-level test control circuit blocks may be structurally identical.
In another, separate embodiment, a hierarchical test control network for an integrated circuit is provided, comprising a plurality of test control circuit blocks in a hierarchical structure having a plurality of hierarchical levels, each of the test control circuit blocks comprising a first test data input port, a second test data input port (referred to in some embodiments as TDI2), and a test data output port, at least one of the test control circuit blocks connected to a chip access port. The test control network further comprises a common test mode select signal connected to each of the test control circuit blocks, a common test reset signal connected to each of the test control circuit blocks, and a common test clock signal connected to each of the test control circuit blocks. The test control circuit blocks at the same hierarchical level are preferably connected in a chain configuration. Test control circuit blocks at the same hierarchical level preferably each receive at their test mode enable input port (e.g., TME_IN) a shared test mode enable signal from the test mode enable output port (e.g., TME_OUT) of a test control circuit block at the immediately higher hierarchical level. The test control circuit blocks in this embodiment may comprise a top-level test control circuit block having a chip access port (CAP) controller connected to the chip access port, and a plurality of lower-level test control circuit blocks, one or more of the lower-level test control circuit blocks at each of the hierarchical levels. At least one of the lower-level test control circuit blocks may be connected to the top-level test control circuit block, and each of the lower-level test control circuit blocks may comprise a socket access port (SAP) controller. Test operation may be transferred downward and upwards within the hierarchical structure by communicating from each test control circuit block to the test control circuit block at the immediately higher or immediately lower hierarchical level in said hierarchical structure.
In another, separate embodiment, a multi-functional test control circuit block is provided, which can operate within a hierarchical test control network, or else be readily configured to operate as a test port controller according to a conventional, standard protocol (such as IEEE Standard 1149.1).
Further embodiments, variations and enhancements are also described herein.